2020 M. Mativenga, S. Lim, F. Haque, and J. Ryu, “Threshold voltage shift-proof circular oxide thin film transistor with top and bottom gates for high bending stability,” Japanese Journal of Applied Physics, 59, 104001 September (2020).
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Negligible threshold-voltage shift is reported for oxide thin-film transistors (TFTs) under high current (3 μA) and tensile bending stress (2 mm
radius). The good stability is attributed to a circular TFT structure with electrically shorted top and bottom gates, and a polyimide substrate
embedded with carbon-nanotubes for mechanical support and damage-free detachment from carrier glass. The circular structure leads to uniform
electric field distribution across the channel, hard saturation in output characteristics, independence from tensile bending direction-related
degradation, as well as isolation of the channel from stress concentrated points, which arise from local electric-field crowding at sharp corners or
channel edges. The double-gate topology increases gate-drivability and achieves volume-accumulation, which minimizes the influence of defects
at the channel surface and slight variations in carrier concentration during stress. Furthermore, the presence of two gates slightly shifts the location
of the neutral bending plane towards the oxide semiconductor, thereby significantly reducing strain. © 2020 The Japan Society of Applied Physics
radius). The good stability is attributed to a circular TFT structure with electrically shorted top and bottom gates, and a polyimide substrate
embedded with carbon-nanotubes for mechanical support and damage-free detachment from carrier glass. The circular structure leads to uniform
electric field distribution across the channel, hard saturation in output characteristics, independence from tensile bending direction-related
degradation, as well as isolation of the channel from stress concentrated points, which arise from local electric-field crowding at sharp corners or
channel edges. The double-gate topology increases gate-drivability and achieves volume-accumulation, which minimizes the influence of defects
at the channel surface and slight variations in carrier concentration during stress. Furthermore, the presence of two gates slightly shifts the location
of the neutral bending plane towards the oxide semiconductor, thereby significantly reducing strain. © 2020 The Japan Society of Applied Physics
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- PrevN. T. T. Hoang, F. Haque, J. Ji, and M. Mativenga, “Fast-Switching Mixed A-Cation Organic-Inorganic Hybrid Perovskite TFTs,” IEEE electron device letters, 40, 6, 917, June (2019).
- NextM. Mativenga, F. Haque, J. G. Um and A. B. Siddik, "Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper," IEEE Transactions on Electron Devices, 67, 8, 3152, August (2020).